The present invention relates to an instruction-issuing circuit, and more particularly to an instruction-issuing circuit that controls out-of-order instruction execution.
A popular method to increase the speed of a pipeline computer is to increase the clock speed and to reduce the time required to execute one instruction. In many cases, to increase the speed of a pipeline computer, the clock speed is increased and, at the same time, the fixed-point operation unit is designed so that it completes one unit of operation within one clock cycle. However, when the clock speed is based on the operation time of the fixed-point operation unit, it sometimes becomes difficult to perform other instruction control operations. In particular, the out-of-order instruction execution mode in which an instruction may be outstripped by another instruction becomes popular these days. This control mode requires more time.
For example, when a one-clock-cycle operation instruction is issued and then a succeeding instruction referencing the result of the preceding one-clock-cycle instruction is issued, all the control operations given below must be completed in one cycle.
(1) From an instruction out-of-order buffer (e.g. Reservation Station), select one instruction to be issued according to some priority. This instruction is one of those whose operands are ready and which can get the resources they require.
(2) Search the instruction out-of-order buffer for the succeeding instructions referencing the result of the selected instruction and set the operand ready flags of those succeeding instructions.
Conventionally, to check whether or not the operands are ready, the tag number attached to an instruction to be issued is compared with that of a succeeding instruction and, if they match, the operands of the succeeding instruction are determined as ready.
To implement out-of-order instruction execution in the conventional technology described above, a check is made to determine whether or not an instruction is ready to be issued and, if it is ready, the operand-ready information must be passed to the succeeding instructions. However, in the conventional system, the number of logic circuit stages required for this processing cannot be reduced any more and, therefore, the LSI manufacturing process prevents the clock speed from increasing.
The present invention seeks to solve the problems associated with the prior art described above. It is an object of the present invention to provide an instruction-issuing circuit which speeds up out-of-order instruction execution and increases the throughput of a pipeline computer.
In one preferred embodiment, each instruction waiting to be issued has an identifier of a succeeding instruction referencing an execution result of the instruction and, when the preceding instruction is issued, an issue condition for the succeeding instruction referencing the execution result of the preceding instruction is updated based on said identifier.